The Wafer Side Of HJT

While fewer, the number of steps for HJT cell processing are completely different from mainstream PERC with change requiring right at the wafer level.

HJT typically uses n-type wafers, unlike today’s mainstream that relies on p-type base wafers. In the past, at least when we published our previous edition of the TaiyangNews HJT Solar Technology report in 2020, the quality of the n-type wafers was very important. The advantages of HJT come primarily from its high Voc of about 750 mV, which is a result of particularly good surface passivation. If anything is limiting the voltage, it is the bulk rather than the surface. Thus, wafers have always been the starting subject of discussions involving HJT. However, such discussions are not so intense anymore. The industry has adopted a heat treatment process similar to annealing to mimic gettering. That’s because there is no involvement of thermal treatment of the wafer with HJT, which eliminates the risk of any change in bulk lifetime during the process. At the same time, the process sequence completely misses the gettering effect in the firing step. Almost every HJT manufacturer is adopting pre-process annealing of the incoming wafers, which has eased the tight spec for wafers. “We buy wafers from the complete ingot; not only that, we buy wafers from all five ingots that are grown from one crucible,” said Po-Chuan Yang, HJT business unit general manager at Risen. The general idea is that this special thermal treatment process relaxes the already tight requirements. That said, some specs have to be met. According to Wenging Wang, CTO of Huasun, a fairly young Chinese company that has quickly become a pioneer in the commercial HJT cell segment, when opting between a wafer lifetime of 2,000 and 3,000 μs, actually the latter is preferred. While there is a steady improvement in lifetimes, high resistivity uniformity is a criterion that the wafer makers are not able to completely honor, said Wang.

Employing larger wafer formats is obviously a very interesting topic in the field of HJT. Unlike with PERC or even TOPCon, adapting HJT to larger wafer formats took some time. The majority of the HJT players have already scaled up their manufacturing to at least M6, and most of these lines are R&D/pilot lines. The next level of the size upgrade is targeted at the new larger-scale production facilities, which are part of every company’s future plan operating in this field. And the manufacturers who have successfully started large-scale manufacturing have skipped M10 and are going directly to G12. Huasun for example has designed its latest 2 GW facility to be G12 compatible. Risen, which has been primarily working on the G1 format, is also jumping to G12 directly, also with its planned new facility (see Progress Of Heterojunction Technology).

But does moving to larger wafer formats with HJT make sense? This was a big concern about a little more than a year ago because, in contrast to batch-type PERC tools, PECVD and PVD – key production equipment used for heterojunction – are based on an inline batch type of setup in which the wafers are processed in carriers. For such tool platforms, larger wafers may not bring in any productivity benefits. Still, there are several benefits beyond tool throughput, according to Huasun’s Wang. The major benefits come in the form of BOM savings at the module level. At the cell level, the first advantage is that the dead zone along the wafer rims, which does not receive any deposition (TCO), is larger with smaller wafers and the ratio of this dead zone to the active area is smaller with larger wafers.

In other words, the utilization of wafer surface area is higher with larger wafers compared to smaller ones. The larger wafer is also relatively less expensive, as the price per unit area is less with larger wafers.

One more important point to note here is edge losses. With HJT, the edge losses for larger wafers, when processed into complete cells and then sliced, are higher compared to PERC. However, instead of processing a full cell, half wafers can be processed; meaning the wafer is sliced into half before cell processing, reducing edge losses. Such an approach would also address the issue of equipment utilization, as a half G12 is very close to M6 in size. The difference is that the shape of the pseudo-square M6 is now changed to a rectangle like format, which just requires carrier adaptation. As already mentioned, Huasun’s new 2 GW facility is optimized to process half G12 wafers. Risen has also upgraded its line to process half G12 wafers, which will also be implemented in its yet-to-be-built GW-scale factory (see HJT Ready For Prime Time).

Risen also worked on the manufacturing standards for G12 half wafers. There are primarily two approaches for making these silicon slices: cutting the wafer into two pieces using lasers or cutting the brick into two, before wafering. The resulting wafers are slightly different in their formats. Laser cutting of the wafer results in chamfers at two edges and two edges without. The half brick method typically results in 4 chamfered edges, though two of them are larger and two smaller. Risen extensively evaluated the wafering process and found that the four-chamfer approach, meaning slicing of the brick before, is optimal as it enables symmetry. The company is also proposing a standard for the chamfer length of 1.41 mm, which it found to provide the best cost-performance ratio. “We hope the supply chain and cell makers would follow the spec that will benefit heterojunction products by cost going down quickly,” said Yang.

The Text is an excerpt from 3^rd edition of TaiyangNews’ Heterojunction Technology 2022 report, which provides an overview on the most recent HJT developments as the technology is entering the GW scale production level and can be accessed free of charge here.