The Core Story Of HJT

As the name itself indicates, layer deposition is the heart of HJT processing. It involves multi-layer stacking of intrinsic-amorphous and doped-amorphous silicon layers of opposite polarities on each side of the wafer and controlling them at the nanometer scale. This is very important as the junction is created at the surface, and the deposited layers also dictate the effectiveness of passivation, which is key for HJT’s high performance. Not only in terms of performance, as much as half of the CapEx required for the entire HJT cell processing line can be attributed to the core layer deposition tools. PECVD and CAT-CVD (an abbreviation for catalytic chemical vapor deposition) have been the two main technologies of choice, while plasma-enhanced atomic layer deposition (PEALD) has been under development.

PECVD is now more or less enjoying a monopoly in the HJT segment. The deposition technology has a vast array of applications, of which TFT display and PV’s very own amorphous silicon deposition tools from the past can also be tweaked for core layer deposition of HJT. Refurbished tools from both the streams have dominated the segment, especially during the initial development phase of HJT. It is the natural path followed by traditional thin-film PV companies that ventured into HJT, at least until the pilot phase. However, with HJT moving into the real commercial phase requiring high productivity systems, the companies are often relying on tool platforms developed specifically for PV. Today’s market offers a wide variety of PECVD tools from different vendors.

A noteworthy development in the field of core layer deposition is the introduction of a microcrystalline silicon layer into the HJT structure. As explained in the above sections, HJT cells consist of intrinsic doped amorphous films sandwiching the wafer substrate. Implementing microcrystalline in the industry only refers to replacing the doped amorphous silicon layers, while very thin intrinsic amorphous silicon films of 1 to 2 nm attached to the wafer surface remain the same. The doped layers of microcrystalline are about 12 to 15 nm in thickness. The primary benefit of using the microcrystalline n-layer applied on an emitter is the lower light absorption coefficient compared to the amorphous silicon layers. The other advantage of microcrystalline is higher conductivity, about 4 to 5 times order of magnitude, thereby reducing the dependence on ITO for conductivity. These benefits reflect in an increase in currents and fill factor, thereby improving the efficiency by about 1.5% relative. Shifting to microcrystalline eases the move towards thinner wafers. “We can go from 150 μm to 130 μm without any loss in efficiency,” said Huasun’s CTO Wenjing Wang (see The Status Quo Of HJT Processing).

Using a microcrystalline doped layer on both sides leads to high field effect passivation. However, today’s context for microcrystalline is only in reference to the front window layer. Chinese cell/module maker Risen’s experience with the 120 μm wafer was a lengthy one in their HJT development activities. Its eventual switch from amorphous silicon to microcrystalline resulted in higher efficiencies, but it is not without downsides. According to Po-Chuan Yang, the main limitation is implementing it in large-scale Risen’s production. Low deposition rates, formation of dust, non-uniformity of the deposited film and low compatibility of VHF plasma are a few issues that need to be addressed before the process enters mass production, said Yang. Until these issues are resolved, PECVD solutions that support both amorphous and microcrystalline will continue to be available, at least for the foreseeable future, believes Yang.

The Text is an excerpt from 3^rd edition of TaiyangNews’ Heterojunction Technology 2022 report, which provides an overview on the most recent HJT developments as the technology is entering the GW scale production level and can be accessed free of charge here.